Handset Processing, Processor Architectures, Coprocessors

As handsets have evolved from simple voice-only analog phones through to complex
3G multimedia platforms, an increasing processing load has been assumed of
the devices. Processing loads and capabilities can be compared using the measurement
of “millions of instructions per second” (MIPS), and device manufacturers
will usually quote the MIPS value for processor chips.

The processing requirement for a 2G GSM phone is in the order of 10 MIPS,
with much of this processing requirement resulting from the voice coding function
(Figure 4.16). The addition of a 2.5G technology such as GPRS raises this figure
to somewhere on the order of 12 MIPS, although the processing complexity of a
2.5G phone will differ significantly across the range of device types encountered,
and may be as high as 40 MIPS.

A UMTS (W-CDMA) handset operating in a 3G network requires a total
processing capability in the region of 500 MIPS, with 40 percent of this requirement
resulting from the relative complexity of the air interface. Adding features,
particularly video processing, will increase the MIPS requirement and there is
already discussion of phones with 1000 MIPS (1 GigaMIP) requirements.
An issue for handset manufacturers and chip designers has always been the
processing limits of DSP chips, which is why handsets typically consist of multiple
processors and hardware accelerators (which remove some of the repetitive tasks
from the DSP and implement these in hardware).


Processor Architectures

The division of tasks between multiple processors within a handset is very common,
and a typical architecture would include a microprocessor (or microcontroller), a
DSP, and hardware accelerators. The role of the hardware accelerator is to remove
from the DSP the more routine repetitive tasks, such as radio channel processing,
leaving the DSP free to focus on other layer 1 tasks and vocoding (implementing a
compression algorithm particular to voice).

In this architecture, the hardware accelerator can be labeled as a coprocessor,
although this is a generic term that may have other meanings in the context of
handsets. Silicon manufacturers have in some cases produced single-chip solutions
that contain the three processing elements; this is an attempt to reduce the area,
volume, and cost of these vital handset components.

The typical task distribution in today’s handsets places the emphasis on the
accelerators rather than the DSP. However, as DSP technology improves, more and
more of the total processing load could be assumed by the DSP, although of course
by that time the evolution of services may be placing even more demands on the
handset processors.

Coprocessors

The spread of processing load has led to a number of different strategies for the
use of coprocessors (Figure 4.18). For example, in a dual-mode 2G/3G phone, a
chip manufacturer might offer a main processor that is responsible for the 2G and
2.5G baseband functions and a companion chip that adds 3G baseband functions.
These two processors can then be coupled to their corresponding radio modules.
This solution is perhaps suited to a manufacturer that is looking to evolve a range
of 2G/2.5G to support 3G capability. The basic core design of the handset can be
reused and the 3G functions are added in parallel. Another possible solution is to
use one processor for all the digital baseband processing and to use a separate coprocessor
to handle specific tasks such as multimedia services.